DC recorder backup

Executed energy and transfer study for a declared 24 V reference load. Hardware has not been built.

Result

The combined-derating case supplies the load for 134.09 s, against a 125 s recording and shutdown target. The nominal model runs for 343.56 s.

With a 2 ms interruption, the minimum modeled output is 23.707 V. The reference recorder minimum is 21.6 V.

The converter regulates 24 V output until its input reaches UVLO; these curves show its input side.

Reference design

Load: 12 W for the first 2 s, then 6 W. Target: 120 s recording plus 5 s shutdown. The model keeps the 6 W load running after the target to measure margin.

Ten 100 F cells in series give 10 F nominal. Combined capacitance factors of 0.8 × 0.8 × 0.9 give 5.76 F. ESR rises from 0.12 to 0.36 ohm, charge starts at 21.6 V and efficiency falls to 82%. These are assumed design corners, not manufacturer ratings.

Functional power path. Component selection and detailed protection remain hardware work.

Calculation and checks

The model solves P = (Vcap − I × ESR) × I and dVcap/dt = −I/C. Load, converter and ESR energy are accumulated independently and checked against the decrease in ½CV². The two load intervals are integrated separately.

All 16 automated tests pass. They include the zero-ESR analytical solution, energy balance, integration refinement, current-limit cutoff, an undersized failing design and transfer-capacitor sensitivity.

case	runtime_s	margin_to_125_s	meets_reference_target	ideal_upper_bound_s	load_energy_j	converter_loss_j	esr_loss_j	energy_residual_j	cutoff
Nominal	343.55981	218.55981	True	345.7566	2073.35887	240.68	6.64585	4.547473508864641e-12	input UVLO
Capacitance tolerance	274.44851	149.44851	True	276.20707	1658.69107	192.53246	5.32423	-2.0463630789890885e-12	input UVLO
Aged capacitance	219.15947	94.15947	True	220.56745	1326.95682	154.01443	4.26696	1.1596057447604835e-11	input UVLO
Cold and aged ESR	339.17105	214.17105	True	345.7566	2047.02631	237.6225	19.72961	7.275957614183426e-12	input UVLO
90% initial charge	261.97281	136.97281	True	264.0443	1583.83687	183.84106	5.80679	3.865352482534945e-12	input UVLO
Combined derating	134.09225	9.09225	True	137.67913	816.55352	183.26622	10.93542	-9.094947017729282e-13	input UVLO
Undersized 20 F cells	25.20505	-99.79495	False	25.94236	163.23032	36.5872	2.33352	2.3860849296397646e-08	input UVLO

Transfer interruption

4700 µF output capacitor, derated to 3760 µF, with 50 mΩ ESR. Constant 12 W load.

Storage comparison

storage	deliverable_energy_to_cutoff_wh	required_load_wh	basis
10 x 100 F series bank, nominal	0.5759330182562789	0.21166666666666667	Integrated ESR and converter model; 24 to 10.5 V input window
10 x 100 F series bank, combined derating	0.22682042316899592	0.21166666666666667	5.76 F, 0.36 ohm, 21.6 V initial, 82% conversion
Generic 19.2 V / 1 Ah battery reference	7.31136	0.21166666666666667	Energy estimate only; no discharge curve, peak current or BMS behavior modeled

The battery row is an energy-only comparison. Its load current capability, discharge curve, protection, charging and life-cycle behavior have not been modeled. It is not a selected or approved battery pack.

Component criteria

item	quantity	criterion	reason
Storage cells	10	100 F nominal, 2.7 V rated each; qualify C >=57.6 F and ESR <=36 milliohm per cell at the declared combined corner	Series equivalent 5.76 F and 0.36 ohm; 24 V maximum bank charge; cell imbalance still requires monitoring
Cell balancing / voltage supervision	1	Monitor and balance all 10 cells; prevent any cell exceeding its qualified voltage/temperature envelope	Bank voltage alone cannot detect cell overvoltage; the virtual bench evaluates declared imbalance and ideal balancing cases
Current-limited charger	1	24 V regulated bank endpoint; limit charge current and monitor temperature; isolate input on source loss	The virtual bench calculates ideal constant-current charging; real inrush and selected-part behavior remain model boundaries
Backup DC/DC stage	1	Regulated 24 V output, >=12 W peak, 10.5 to 24 V input, >=82% at worst corner, 2 A input capability	Efficiency and UVLO assumptions must be checked on selected parts across load and temperature
Power-path isolation	2	Reverse-blocking paths on main supply and backup output; voltage/current ratings after transient measurement	Model assumes ideal reverse isolation; no measured backfeed result
Output hold-up capacitor	1	4700 microfarad nominal, >=3760 microfarad minimum, <=50 milliohm ESR; >=35 V voltage rating subject to transient qualification	Supports assumed 2 ms source transfer at 12 W
Protection and shutdown	1	Fuse/current limit sized against chosen conductors, short-circuit behavior and stored energy; recorder power-fail signal and verified shutdown acknowledgment	Electrical continuity cannot prove file-system integrity

Limits and next hardware checks

No physical circuit, PCB, purchased components or bench measurements are included. Values are reference qualification targets.
The regulator is ideal apart from fixed efficiency, idle load, ESR, current limit and UVLO. The virtual bench adds reduced leakage, imbalance and charging models. Loop stability, actual thermal rise and selected-part dropout behavior remain outside the model.
The 2 ms transfer interruption is an assumed requirement. Reverse blocking is a topology requirement, not a measured backfeed result.
Recorder file integrity and shutdown completion need tests on the actual device. A passing energy calculation does not establish either.

bench_acceptance.md records the unexecuted bench checks. Read results/summary.json, test-log.txt and verification.json for the executed evidence.

Source and reproduction

Method reference: Analog Devices, Energy Storage Using Supercapacitors. It informs loss and degradation treatment; numerical inputs here are separately declared assumptions.

python -m pip install -r requirements.txt
python run.py
python -m unittest -v

Virtual validation

Executed synthetic and theoretical run-through. The report includes cases, acceptance results and model boundaries.