Outage recorder backup

Implementation

Constant-power nonlinear discharge with ESR, converter losses, input current limit and UVLO

Time-domain output-capacitor transfer model

Storage comparison, component criteria and functional schematic

Executed synthetic/theoretical validation with a selected operating envelope, adverse conditions, and reproducible acceptance evidence.

Inputs and assumptions

• 12 W for 2 s, then 6 W; 125 s recording/shutdown target
• All component and recorder values are declared reference assumptions; no hardware measurements

Results

Report figures (4)

Open the full report ↗

Verification

16 tests; analytical runtime, energy conservation, step refinement and deliberately failing storage case. Additional virtual validation: 13 checks matched their expected outcomes. Adverse design conditions remain in the results.

python run.py

Project files

The ZIP contains the source, inputs, results, and instructions. These files are also available individually.

• Study reportreport.html · 9 KB
• Discharge and transfer solvermodel.py · 5 KB
• Reference inputsinputs.json · 1 KB
• Component criteriacomponent_criteria.csv · 2 KB
• Calculated design cornersresults/sensitivity.csv · 1 KB
• Storage comparisonresults/storage_comparison.csv · 1 KB
• Verification casestest_model.py · 3 KB
• Unexecuted bench procedurebench_acceptance.md · 2 KB
• Virtual validation reportvirtual-validation.html · 8 KB
• Completion evidence and source hashescompletion.json · 6 KB
• Reproducible virtual validationvirtual_commissioning.py · 13 KB
• Executed acceptance matrixresults/virtual-acceptance.csv · 3 KB
• Selected numerical design envelopeselected-operating-envelope.json · 1 KB
• Component-corner runtime and ideal shunt-balanced chargefigures/virtual-power-bench.svg · 38 KB
• 64 component cornersresults/virtual-component-corners.csv · 5 KB
• Transfer tolerance sweepresults/virtual-transfer-corners.csv · 1 KB
• Charge and shunt fault casesresults/virtual-charge-cases.csv · 1 KB
• Leakage and resistor tradeoffresults/virtual-passive-balance.csv · 1 KB
• Synthetic recording and checkpoint outcomesresults/virtual-recorder-shutdown.csv · 1 KB
• Operating enveloperesults/virtual-summary.json · 1 KB

Run locally

Python 3.11+ / NumPy / SciPy / Matplotlib

Extract the ZIP and open a terminal in the dc-recorder-backup folder. The README includes setup and usage details.

python -m pip install -r requirements.txt
python run.py
python -m unittest -v

Limits

• No physical circuit, PCB, purchased components or bench measurements are included. Values are reference qualification targets.
• The regulator is ideal apart from fixed efficiency, idle load, ESR, current limit and UVLO. The virtual bench adds reduced leakage, imbalance and charging models. Loop stability, actual thermal rise and selected-part dropout behavior remain outside the model.
• The 2 ms transfer interruption is an assumed requirement. Reverse blocking is a topology requirement, not a measured backfeed result.
• Recorder file integrity and shutdown completion need tests on the actual device. A passing energy calculation does not establish either.