# DC recorder backup

An executed calculation package for a reference 24 V recorder, with nonlinear capacitor discharge, loss accounting, output hold-up, design corners and verification. This is a completed numerical study, not a built power supply.

## Run

Python 3.11 or later:

```sh
python -m venv .venv
# Linux/macOS: source .venv/bin/activate
# Windows: .venv\Scripts\activate
python -m pip install -r requirements.txt
python run.py
python -m unittest -v
```

Open `report.html` directly. No server or internet is required after dependency installation. `run.py` regenerates results, figures, verification and the report; it exits on a failing test. `verification.json` records exact executed test names and Python source hashes.

## Inputs and methods

`inputs.json` declares the recorder, storage and transfer assumptions. `model.Case` declares the converter's default UVLO, current limit and load timing. The reference load is 12 W for 2 s and 6 W afterward; it must stay powered for 120 s recording plus 5 s shutdown. Discharge continues after that target to measure runtime.

The ten-cell, 100 F-per-cell series bank has 10 F nominal capacitance. The combined corner uses 5.76 F, 0.36 ohm ESR, 21.6 V initial charge and 82% fixed converter efficiency. Those are analyst-selected qualification envelopes, **not extracted component ratings**. Change both nominal/worst inputs when using another bank; the separately stated derating factors document this reference selection.

The ODE uses the stable current root of `Pin = (Vcap − I R) I` and `dV/dt = −I/C`. Integration stops at input UVLO or current limit. Separately integrated load, converter and ESR energies reconcile against lost capacitor energy. A zero-ESR analytical energy result and step refinement check the numerical calculation.

The output-transfer model discharges a derated capacitor into the peak constant-power load through ESR. A 2 ms source interruption is assumed. Supply isolation is shown in `figures/functional-schematic.svg`; backfeed is not simulated or measured.

CSV outputs can be opened in spreadsheet software. `results/sensitivity.csv` is a calculated corner comparison, not an interactive workbook. `results/storage_comparison.csv` compares the bank to a generic battery energy estimate; it does not claim a qualified battery design.

## Limits

No selected controller, layout, physical hardware, measured thermal response, reverse-current test or physical recorder integrity test. Converter regulation is ideal until cutoff. The virtual bench adds reduced charging, imbalance, leakage balancing and recorder timing models. `component_criteria.csv` provides selection criteria; `bench_acceptance.md` separates unexecuted hardware checks from completed numerical tests.

Method reference: [Analog Devices, Energy Storage Using Supercapacitors](https://www.analog.com/en/resources/analog-dialogue/raqs/raq-issue-179.html). Capacitance, ESR and conversion loss all affect usable hold-up energy; the reference numbers are declared separately in this package.

## Completed virtual bench

`python run.py` also runs 64 component corners, a transfer tolerance sweep, cell-imbalance and ideal balancing models, leakage-resistor tradeoffs and a synthetic recorder shutdown sequence. Open `virtual-validation.html`. Fifty-seven of the 64 corners meet 125 s; seven adverse corners do not. At the declared combined corner, the modeled steady-load boundary is 6.433 W. The 24 V/3760 microfarad/50 milliohm transfer boundary is 16.938 ms to 21.6 V.

One 80 F cell in series with nine 120 F cells would reach 3.429 V at a 24 V bank endpoint without balancing. The sufficient ideal shunt holds 2.65 V; an undersized shunt still exceeds 2.7 V. The timing model distinguishes acknowledged and interrupted recorder checkpoints. These are modeled outcomes, not component or data-integrity measurements.

`completion.json` records 13 executed acceptance checks and hashes. Four additional regression tests bring the package total to 16. Each sweep is available as CSV under `results/virtual-*`.

`selected-operating-envelope.json` records the accepted numerical design: at least 5.76 F, no more than 0.36 ohm ESR, initial bank at least 21.6 V, efficiency at least 82%, UVLO at most 10.5 V, and a load of 12 W for 2 s then at most 6 W. The output-capacitor transfer is limited to 2 ms. Cell charging uses the declared adequate ideal shunt. Higher-load/UVLO corners and insufficient balancing are rejected rather than included in the accepted envelope.